1. Field of the Invention
The present invention relates to a multilayer gate oxide, and more particularly to a semiconductor structure with a multilayer gate oxide and method of fabricating the same.
2. Description of the Prior Art
Field effect transistors (FETs) are commonly used in conventional integrated circuit (IC) design. Due to shrinking technology nodes, devices and shrinking ground rules are the keys to enhance performance and to reduce cost.
In standard MOS devices, silicon oxide is the standard gate dielectric. As the devices are scaled down, the gate dielectric needs to become thinner. The gate dielectric is formed by a thermal oxidation process, since this kind of silicon oxide has better quality. For next generation devices, the thickness of the silicon oxide has to be much smaller than before. Silicon oxide made by thermal oxidation will have pin holes when its thickness is shrunk down to a certain level, however, and the quality of will be deteriorated.
Therefore, a method of making silicon oxide having fewer pin holes is needed.